It is known to provide switched network processor architectures in which both ingress and egress data structures are accessible and manageable by control plane software executing on a single side (typically the egress side) of a network processor. This is possible due to a lack of a hard boundary between the data structures on the two sides of the processor. The IBM PowerNP NP4GS3 is an example of such a network processor.
FIG. 1 is a schematic representation of a network processor 100 (e.g., the NP4GS3) having a switched architecture in which processing resources are shared between egress and ingress sides. Network processor 100 includes an ingress side 105 and an egress side 110, each having a set of communication ports 115 (e.g., data movers or DM), a set of processing resources 120 (e.g., core language processors or CLP) and a control 125 (e.g., guided frame handler or GFH). Additionally, it is common to provide additional functionality on one side that is not duplicated on the other side. For example, the NP4GS3 includes a general table handler (GTH) 130 for handling tree management commands.
Network processor 100 provides for a logical boundary between egress side 110 and ingress side 105 with all data structures residing on the same physical memories. The logical grouping of data structures may be structured in several different ways but in the NP4GS3, the logical grouping of data structures into an ingress category or an egress category is based upon when the data structures are accessed in a forwarding path.
One advantage to grouping the data structures by logical boundaries instead of physical boundaries is that a control point is able to create/initialize all data structures (e.g., both egress and ingress categories) by directing control plane messages, carrying appropriate management commands, to a single side of the network processor for processing. In the NP4GS3, this single side is typically the egress side because the egress side is constructed in such a way that there is greater resource availability on the egress side.
However, there are some network processors that have switched architectures in which the ingress/egress split occurs on physical boundaries and not logical boundaries. FIG. 2 is a schematic representation of a network processor 200 having a switched architecture in which processing resources are split between an ingress side 205 and an egress side 210. Network processor 200 has a hard boundary between egress and ingress data structures inhibiting egress software from directly accessing ingress data structures (as well as inhibiting ingress software from directly accessing egress data structures). Network processor 200 is designed to function collectively as a single network processor though many discrete functional units may implement the processor, with the discrete units communicated to each other. Network processor 200 includes discrete processing resources on ingress side 205 and on egress side 210, with an internal communication channel from egress side 210 to ingress side 205 identified as wrap 215. Both ingress side 205 and egress side 210 have separate physical memories 220, control stores 225, a network processing unit 230, among other processing resources.
While there are many advantages to designing network processor 200 in this way, it requires a different creation/initialization method from the control point method described with respect to network processor 100.
Since the ingress and egress memories/processing engines are physically separated in network processor 200, in order to create/initialize data structures on a particular side of network processor 200, a control point must direct appropriate control plane messages explicitly to that particular side. Control plane software executing on network processor 200 is perfectly able to efficiently create and initialize the desired data structures on the appropriate side.
Network Processor Management Software executing on the control point decides on location, structure, size and properties of the Network Processor data structures such as, for example, forwarding tables. A control point operating in a homogenous network having either type of network processor described above can readily send appropriate control plane messages to create and initialize both ingress and egress data structures. In a heterogeneous, or mixed, configuration of network processors, the network processor management software has to be sensitive to the fact that any particular network processor may have one of two or more different architectures.
Accordingly, what is needed is a method and system for providing network processor management that efficiently operates in homogenous and heterogonous environments. The present invention addresses such a need.